The present invention relates to the field of semiconductor fabrication, and more particularly, to integrated circuits with structures that reduce or prevent damage to integrated circuits.
An integrated circuit is formed on a die, which is typically a semiconductor substrate. During the manufacture and operation of the integrated circuit, the die is subjected to mechanical stress. As the die is stressed, active devices, passive devices, and interconnects that make up the integrated circuit are also stressed. For example, during the bonding, such as flip-chip bonding, of a die to a substrate the die and the substrate are exposed to heat, which causes the substrate and the die to expand. If the die and the substrate have different coefficients of thermal expansion, the die and the substrate expand at different rates which subjects the die to mechanical stress. The stress may be especially high near the edges and the corners of the die. When the die is stressed, the active devices, the passive devices, and the interconnects formed on the die are also stressed, which may cause a mechanical failure of the devices or the interconnects. One type of mechanical failure that results from mechanical stress applied to a die is the shearing of interconnects. Interconnects generally connect devices, such as active and passive devices, together in the integrated circuit. Shearing the connections between devices in the integrated circuit causes catastrophic failure of the integrated circuit.
For some types of integrated circuits that will be developed in the next generation of integrated circuits, the dielectric surrounding each interconnect will be a high strength material, such as an oxide. For these types of integrated circuits, catastrophic failure of the integrated circuit from mechanical stress may remain relatively small. However, for many types of next generation integrated circuits, such as processors, the interconnects will be fabricated from high conductivity materials, such as copper, embedded in low strength dielectric materials, such as low-K materials. For these types of integrated circuits, stress induced catastrophic failures, such as interconnect shearing, will most likely increase.
For these and other reasons, there is a need for the present invention.